Oct. 4, 2012
우리 연구실에서 "A 25-Gb/s 5-mW CMOS CDR/Deserializer"라는 주제로 세미나를 개최하였습니다.

일시 : 2012년 10월 4일(목) 16:00 ~ 18:00

장소 : 우리별세미나실 ( 정보전자동 6층구간 2201호 )

주제 : A 25-Gb/s 5-mW CMOS CDR/Deserializer

연사 : 정준원 박사(University of California, Los Angeles)


Recent studies indicate that the input/output bandwidth of serial links must
increase by 2 to 3 times every two years so as to keep up with the demand for
higher data rates. In order to manage such bandwidths with reasonable power
consumption, an efficiency of around 1 mW/Gb/s for the overall
transceiver is targetted , necessitating a much smaller value for each building block.

Among the power-hungry functions in a broadband receiver, clock and
data recovery (CDR) as well as data deserialization prominently stand out.
These functions incorporate a large number of high-speed latches and
frequency dividers, consuming the lion's share of the power.

This presentation describes the design of a 25-Gb/s CDR circuit and a
deserializer that, through the use of ``charge steering'' and other innovations,
achieve a twenty-fold reduction in the power dissipation with respect to the
prior art. Realized in TSMC's 65-nm CMOS technology, an experimental
prototype exhibits an integrated clock jitter of 1.52 ps,rms and a jitter
tolerance of 0.5 unit interval (UI) at a jitter frequency of 5 MHz.