Intelligent Processor

Applications like self-driving car, wearable device, and Internet-of-Things (IoT) are key technologies that will lead us to upcoming true intelligent world. Future systems must employ a brain-like intelligent processor that can efficiently process these applications, especially under the mobile environment. Our MVLSI Multimedia Processor group focuses on the VLSI implementation of an energy-efficient intelligent processor. Deep neural network algorithms such as Convolutional Neural Network and Recurrent Neural Network are our primary target for the implementation of a highly-accurate, yet energy-efficient intelligent processor. Such an efficient processor can be realized through a careful algorithm-architecture-circuit co-optimization. A highly-efficient memory architecture that can meet huge memory requirements of deep neural network algorithms is another ongoing study topic as well.

Interface Circuit

Recently, as an enormous effort on transferring multimedia data faster increases, the demand of fast serial link transceiver design becomes higher. Although SiGe or BiCMOS processes are previously used for the optical transceiver designs, CMOS-based multi-dozen GHz transceiver leads the future waves due to the price and power efficiency. Furthermore, technologies about XDR (eXtreme Data Rate) and DDR3 (Double Data Rate 3) which maximize the data bandwidth between CPU and memory, and technologies about PCI Express Bus which minimizes the bottleneck effects between the graphic card and the main board become more popular. Since these technologies are wholly based on highly fast CMOS serial link transceiver design, Interface Circuit group researches on circuit blocks to transmit signals faster with lower power / higher performance, especially, Clock & Data Recovery (CDR) circuit, Phase Locked Loop (PLL), Delay Locked Loop (DLL), High-Speed logic styles, Low-Power circuit techniques.