Accepted for publication |
|
Yunki Han, Jaekang Shin, Gunhee Park, Lee-Sup Kim
|
| CoCoA: Algorithm-Hardware Co-Design for Large-Scale GNN Training using Compressed Graph |
| IEEE/ACM International Conference On Computer Aided Design, 2024 |
| |
|
Junyoung Park, Myeonggu Kang, Yunki Han, Yanggon Kim, Jaekang Shin, Lee-Sup Kim
|
| Token-Picker: Accelerating Attention in Text Generation with Minimized Memory Transfer via Probability Estimation (Best Paper Award) |
| IEEE/ACM Design Automation Conference, 2024 |
| |
2023 |
|
Junkyum Kim, Myeonggu Kang, Yunki Han, Yanggon Kim, Lee-Sup Kim
|
| OptimStore: In-Storage Optimization of Large Scale DNNs with On-Die Processing |
| IEEE International Symposium on High-Performance Computer Architecture, Feb 2023 |
| |
2022 |
|
Hyein Shin, Myeonggu Kang, Lee-Sup Kim
|
| Re2fresh: A Framework for Mitigating Read Disturbance in ReRAM-based DNN Accelerators |
| IEEE/ACM International Conference On Computer Aided Design, Nov 2022 |
| |
|
Jaekang Shin, Seungkyu Choi, Jongwoo Ra, Lee-Sup Kim
|
| Algorithm/Architecture Co-Design for Energy-Efficient Acceleration of Multi-Task DNN |
| IEEE/ACM Design Automation Conference, Jul 2022 |
| |
2021 |
|
Hancheon Yun, Hyein Shin, Myeonggu Kang, Lee-Sup Kim
|
| Optimizing ADC Utilization through Value-Aware Bypass in ReRAM-based DNN Accelerator |
| IEEE/ACM Design Automation Conference, Dec 2021 |
| |
|
Hyein Shin, Myeonggu Kang, Lee-Sup Kim
|
| Fault-free: A Fault-resilient Deep Neural Network Accelerator based on Realistic ReRAM Devices |
| IEEE/ACM Design Automation Conference, Dec 2021 |
| |
|
Seungkyu Choi, Jaekang Shin, Lee-Sup Kim
|
| A Convergence Monitoring Method for DNN Training of On-Device Task Adaptation |
| IEEE/ACM International Conference On Computer Aided Design, Nov 2021 |
| |
|
Kangkyu Park, Yunki Han, Lee-Sup Kim
|
| Deferred Dropout: An Algorithm-Hardware Co-Design DNN Training Method Provisioning Consistent High Activation Sparsity |
| IEEE/ACM International Conference On Computer Aided Design, Nov 2021 |
| |
|
Myeonggu Kang, Hyein Shin, Jaekang Shin, Lee-Sup Kim
|
| A Framework for Area-efficient Multi-task BERT Execution on ReRAM-based Accelerators |
| IEEE/ACM International Conference On Computer Aided Design, Nov 2021 |
| |
2020 |
|
Hyein Shin, Myeonggu Kang, Lee-Sup Kim
|
| Thermal-aware Optimization Framework for ReRAM-based Deep Neural Network Acceleration |
| IEEE/ACM International Conference On Computer Aided Design, Nov 2020 |
| |
|
Jaekang Shin, Seungkyu Choi, Yeongjae Choi, Lee-Sup Kim
|
| A Pragmatic Approach to On-device Incremental Learning System with Selective Weight Updates |
| IEEE/ACM Design Automation Conference , Jul 2020 |
| |
2019 |
|
Hyein Shin, Jaehyeong Sim, Daewoong Lee, Lee-Sup Kim
|
| A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural Networks |
| IEEE/ACM International Conference On Computer Aided Design, Nov 2019 |
| |
|
Youngbeom Jung, Yeongjae Choi, Jaehyeong Sim, Lee-Sup Kim
|
| eSRCNN: A Framework for Optimizing Super-Resolution Tasks on Diverse Embedded CNN Accelerators |
| IEEE/ACM International Conference On Computer Aided Design, Nov 2019 |
| |
|
Kyeonghan Kim, Hyein Shin, Jaehyeong Sim, Myeonggu Kang, Lee-Sup Kim
|
| An Energy-efficient Processing-in-memory Architecture for Long Short Term Memory in Spin Orbit Torque MRAM |
| IEEE/ACM International Conference On Computer Aided Design, Nov 2019 |
| |
|
Seungkyu Choi, Jaehyeong Sim, Myeonggu Kang, Yeongjae Choi, Hyeonuk Kim, Lee-Sup Kim
|
| A 47.4uJ/epoch Trainable Deep Convolutional Neural Network Accelerator for In-Situ Personalization on Smart Devices |
| IEEE Asian Solid-State Circuits Conference, Nov 2019 |
| |
|
Hyeonwook Wi, Hyeonuk Kim, Seungkyu Choi, Lee-Sup Kim
|
| Compressing Sparse Ternary Weight Convolutional Neural Networks for Efficient Hardware Acceleration |
| ACM/IEEE International Symposium on Low Power Electronics and Design, Jul 2019 |
| |
|
Daewoong Lee, Dongil Lee, Yong-Hun Kim, Lee-Sup Kim
|
| A 0.87 V 12.5 Gb/s Clock-Path Feedback Equalization Receiver with Unfixed Tap Weighting Property in 65 nm CMOS |
| Symposium on VLSI Circuits, Jun 2019 |
| |
|
Seungkyu Choi, Jaekang Shin, Yeongjae Choi, Lee-Sup Kim
|
| An Optimized Design Technique of Low-bit Neural Network Training for Personalization on IoT Devices |
| IEEE/ACM Design Automation Conference, Jun 2019 |
| |
|
Hyeonuk Kim, Jaehyeong Sim, Yeongjae Choi, Lee-Sup Kim
|
| NAND-Net: Minimizing Computational Complexity of In-Memory Processing for Binary Neural Networks |
| IEEE International Symposium on High-Performance Computer Architecture, Jan 2019 |
| |
2018 |
|
Jaehyeong Sim, Hoseok Seol, Lee-Sup Kim
|
| NID: Processing Binary Convolutional Neural Network in Commodity DRAM |
| ACM/IEEE International Conference On Computer Aided Design, Nov 2018 |
| |
|
Seungkyu Choi, Jaehyeong Sim, Myeonggu Kang, Lee-Sup Kim
|
| TrainWare: A Memory Optimized Weight Update Architecture for On-Device Convolutional Neural Network Training |
| ACM/IEEE International Symposium on Low Power Electronics and Design, Jul 2018 |
| |
2017 |
|
|
| A DLL-based Reference-less CDR with ISI Jitter Reduction Scheme |
| 2017 IDEC SoC Congress Chip Design Contest Best Design Award , Jun 2017 |
| |
|
Hyeonuk Kim, Jaehyeong Sim, Yeongjae Choi, Lee-Sup Kim
|
| A Kernel Decomposition Architecture for Binary-weight Convolutional Neural Networks |
| ACM/IEEE Design Automation Conference, Jun 2017 |
| |
|
Yeongjae Choi, Jun-Seok Park, Lee-Sup Kim
|
| Hardware-Centric Vision Processing for Mobile IoT Environment Exploiting Approximate Graph cut in Resistor Grid |
| IEEE Winter Conference on Applications of Computer Vision, May 2017 |
| |
|
Myunghoon Choi, Seungkyu Choi, Jaehyeong Sim, Lee-Sup Kim
|
| SENIN: An Energy-Efficient Sparse Neuromorphic System |
| The International Symposium on Low Power Electronics and Design , May 2017 |
| |
2016 |
|
Hoseok Seol, Wongyu Shin, Jaemin Jang, Jungwhan Choi, Jinwoong Suh, Lee-Sup Kim
|
| Energy Efficient Data Encoding in DRAM channels exploiting Data Value Similarity |
| International Symposium on Computer Architecture, Jun 2016 |
| |
|
Minhye Kim, Soo-Chang Chae, Young-Ju Kim, Seung-Jun Bae, Lee-Sup Kim
|
| Crosstalk Avoidance Code for Direct Pass-Through Architecture |
| IEEE International Symposium on Circuits and Systems, May 2016 |
| |
|
Jaehyeong Sim, Jun-Seok Park, Minhye Kim, Dongmyung Bae, Yeongjae Choi, Lee-Sup Kim
|
| A 1.42TOPS/W Deep Convolutional Neural Network Recognition Processor for Intelligent IoE Systems |
| IEEE International Solid-State Circuit Conference, Feb 2016 |
| |
2015 |
|
Dongil Lee, Taeho Lee, Yong-Hun Kim, Young-Ju Kim, Lee-Sup Kim
|
| An Injection Locked PLL for Power Supply Variation Robustness Using Negative Phase Shift Phenomenon of Injection Locked Frequency Divider |
| IEEE Custom Integrated Circuits Conference, Sep 2015 |
| |
|
Jungwhan Choi, Wongyu Shin, Jaemin Jang, Jinwoong Suh, Yongkee Kwon, Youngsuk Moon, Lee-Sup Kim
|
| Multiple Clone Row DRAM: A Low Latency and Area Optimized DRAM |
| International Symposium on Computer Architecture, Jun 2015 |
| |
|
Daewoong Lee, Dongil Lee, Taeho Lee, Yong-Hun Kim, Lee-Sup Kim
|
| An Integrated Time Register and Arithmetic Circuit with Combined Operation for Time-Domain Signal Processing |
| IEEE International Symposium on Circuits and Systems, May 2015 |
| |
2014 |
|
Jaehyeong Sim, Jun-Seok Park, Seungwook Paek, Lee-Sup Kim
|
| Timing Error Masking by Exploiting Operand Value Locality in SIMD Architecture (Best Paper Award) |
| IEEE International Conference on Computer Design, Oct 2014 |
| |
|
Wongyu Shin, Seungwook Paek, Lee-Sup Kim
|
| An Area-Efficient on-Chip Temperature Sensor with Nonlinearity Compensation Using Injection-Locked Oscillator (ILO) |
| IEEE International Symposium on Circuits and Systems, Jun 2014 |
| |
|
Wongyu Shin, Jeongmin Yang, Jungwhan Choi, Lee-Sup Kim
|
| NUAT: A Non-Uniform Access Time Memory Controller (Best Paper Runner-up) |
| IEEE International Symposium on High-Performance Computer Architecture, Feb 2014 |
| |
2013 |
|
Young-Ju Kim, Lee-Sup Kim
|
| A 12Gb/s 0.92mW/Gb/s Forwarded Clock Receiver based on ILO with 60MHz Jitter Tracking Bandwidth Variation Using Duty Cycle Adjuster in 65nm CMOS |
| IEEE Symposium on VLSI Circuits, Jun 2013 |
| |
|
Jeongmin Yang, Young-Ju Kim, Lee-Sup Kim
|
| A 7 mW 2.5 GHz Spread Spectrum Clock Generator Using Switch-Controlled Injection-Locked Oscillator |
| IEEE International Symposium on Circuits and Systems, May 2013 |
| |
|
Jihwan Seol, Young-Ju Kim, Sang-Hye Chung, Kyung-Soo Ha, Seung-Jun Bae, Jung-Bae Lee, Joo Sun Choi, Lee-Sup Kim
|
| An 8Gb/s 0.65mW/Gb/s Forwarded Clock Receiver Using an ILO with Dual Feedback Loop and Quadrature Injection Scheme |
| IEEE International Solid-State Circuit Conference, Feb 2013 |
| |
|
Seungwook Paek, Wongyu Shin, Jaeyoung Lee, Hyo-Eun Kim, Jun-Seok Park, Lee-Sup Kim
|
| All-Digital Hybrid Temperature Sensor Network for Dense Thermal Monitoring |
| IEEE International Solid-State Circuit Conference, Feb 2013 |
| |
2012 |
|
Hyo-Eun Kim, Jun-Seok Park, Jae-Sung Yoon, Seok-Hoon Kim, Lee-Sup Kim
|
| A 1mJ/frame Unified Media Application Processor with a 179.7pJ Mixed-Mode Feature Extraction Engine for Embedded 3D-Media Contents Processing |
| IEEE Custom Integrated Circuits Conference, Sep 2012 |
| |
|
Sang-Hye Chung, Lee-Sup Kim
|
| A 1.22mW/Gb/s 9.6Gb/s Data Jitter Mixing Forwarded-Clock Receiver Robust against Power Noise with 1.92ns Latency Mismatch between Data and Clock in 65nm CMOS |
| IEEE Symposium on VLSI Circuits, Jun 2012 |
| |
|
Seungwook Paek, Seok-Hwan Moon, Wongyu Shin, Jaehyeong Sim, Lee-Sup Kim
|
| PowerField: A Transient Temperature-to-Power Technique based on Markov Random Field Theory |
| ACM/IEEE Design Automation Conference, Jun 2012 |
| |
|
Yong-Hun Kim, Lee-Sup Kim
|
| A 20 Gbps 1-Tap Decision Feedback Equalizer with Unfixed Tap Coefficient |
| IEEE International Symposium on Circuits and Systems, May 2012 |
| |
2011 |
|
Young-Ju Kim, Sang-Hye Chung, Lee-Sup Kim
|
| A 7.4Gb/s Forwarded Clock Receiver Based on First-Harmonic Injection-Locked Oscillator Using AC Coupled Clock Multiplication Unit in 0.13um CMOS |
| IEEE Custom Integrated Circuits Conference, Oct 2011 |
| |
|
Won-Young Lee, Lee-Sup Kim
|
| A 5.4 Gb/S Clock and Data Recovery Circuit Using the Seamless Loop Transition Scheme Without Phase Noise Degradation |
| IEEE International Symposium on Circuits and Systems, May 2011 |
| |
|
Seungwook Paek, Jiehwan Oh, Sang-Hye Chung, Lee-Sup Kim
|
| Area-Efficient Dynamic Thermal Management Unit Using MDLL with Shared DLL Scheme for Many-Core Processors |
| IEEE International Symposium on Circuits and Systems, May 2011 |
| |
|
Sang-Hye Chung, Kyung-Soo Ha, Lee-Sup Kim
|
| An 8Gb/s Forwarded-Clock I/O Receiver with up to 1GHz Constant Jitter Tracking Bandwidth Using a Weak Injection-Locked Oscillator in 0.13um CMOS |
| IEEE Symposium on VLSI Circuits, May 2011 |
| |
|
Hyo-Eun Kim, Jae-Sung Yoon, Kyu-Dong Hwang, Young-Jun Kim, Jun-Seok Park, Lee-Sup Kim
|
| A 275mW Heterogeneous Multimedia Processor for IC-Stacking on Si-Interposer |
| IEEE International Solid-State Circuit Conference, Feb 2011 |
| |
2010 |
|
Hong-Yun Kim, Young-Jun Kim, Lee-Sup Kim
|
| Reconfigurable Mobile Stream Processor for Ray Tracing |
| IEEE Custom Integrated Circuits Conference, Sep 2010 |
| |
|
Mi-Jo Kim, Lee-Sup Kim
|
| A 100MHz-to-1GHz Open-Loop ADDLL with Fast Lock-Time for Mobile Applications |
| IEEE Custom Integrated Circuits Conference, Sep 2010 |
| |
|
Hyunkyu Jeon, Yong-Whan Moon, Lee-Sup Kim, Jeong-Il Seo
|
| A Clock-Embedded Voltage Differential Signaling (CVDS) for Chip-On-Glass Application of TFT-LCDs |
| Society of Information Display Symposium , Jun 2010 |
| |
|
Kyu-Dong Hwang, Lee-Sup Kim
|
| An Area Efficient Asynchronous Gated Ring Oscillator TDC With Minimum GRO Stages |
| IEEE International Symposium on Circuits and Systems, May 2010 |
| |
|
Sang-Hye Chung, Kyu-Dong Hwang, Won-Young Lee, Lee-Sup Kim
|
| A High Resolution Metastability-Independent Two-Step Gated Ring Oscillator TDC with Enhanced Noise Shaping |
| IEEE International Symposium on Circuits and Systems, May 2010 |
| |
|
Jae-Sung Yoon, Jeonghyun Kim, Hyo-Eun Kim, Won-Young Lee, Seok-Hoon Kim, Kyusik Chung, Jun-Seok Park, Lee-Sup Kim
|
| A Graphics and Vision Unified Processor with a 0.89uW/fps Pose Estimation Engine for Augmented Reality |
| IEEE International Solid-State Circuit Conference , Feb 2010 |
| |
2009 |
|
Seok-Hoon Kim, Hong-Yun Kim, Young-Jun Kim, Kyusik Chung, Donghyun Kim, Lee-Sup Kim
|
| A 116fps 74mW Mobile Heterogeneous 3D-Media Processor for 3D Display Contents |
| IEEE Symposium on VLSI Circuits , Jun 2009 |
| |
|
Hyeyoon Joo, Kyung-Soo Ha, Lee-Sup Kim
|
| A Data Pattern-Tolerant Adaptive Equalizer Using Spectrum Balancing Method |
| IEEE Symposium on VLSI Circuits , Jun 2009 |
| |
|
Hyunkyu Jeon, Lee-Sup Kim
|
| A Clock Embedded Differential Signaling (CEDS) for the Next Generation TFT-LCD Applications in Multi-Core Systems |
| Society of Information Display Symposium , Jun 2009 |
| |
|
Young-Jun Kim, Kyusik Chung, Lee-Sup Kim
|
| Bank-Partition and Multi-Fetch Scheme for Floating-Point Special Function Units in Multi-Core Systems |
| IEEE International Symposium on Circuits and Systems , May 2009 |
| |
|
Won-Young Lee, Lee-Sup Kim
|
| A Spread Spectrum Clock Generator with Spread Ratio Error Reduction Scheme for DisplayPort Main Link |
| IEEE International Symposium on Circuits and Systems , May 2009 |
| |
|
Kyung-Soo Ha, Lee-Sup Kim
|
| A 6Gb/s/pin Pseudo-Differential Signaling Using Common-Mode Noise Rejection Techniques without Reference Signal for DRAM Interfaces |
| IEEE International Solid-State Circuit Conference , Feb 2009 |
| |
2008 |
|
Kyung-Soo Ha, Lee-Sup Kim
|
| A 3.2-Gb/s Transceiver with a Quarter-Rate Linear Phase Detector reducing the phase offset |
| IEEE Asian Solid-State Circuit Conference , Nov 2008 |
| |
|
Kwangil Oh, Lee-Sup Kim
|
| A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme |
| IEEE Custom Integrated Circuits Conference , Oct 2008 |
| |
|
Jae-Sung Yoon, Donghyun Kim, Changhyo Yu, Lee-Sup Kim
|
| A 3D Graphics Processor with Fast 4D Vector Inner Product Units and Power Aware Texture Cache |
| IEEE Custom Integrated Circuits Conference , Oct 2008 |
| |
|
Kyusik Chung, Changhyo Yu, Donghyun Kim, Lee-Sup Kim
|
| Tessellation-Enabled Shader for a Bandwidth-Limited 3D Graphics Engine |
| IEEE Custom Integrated Circuits Conference , Oct 2008 |
| |
|
Hyunkyu Jeon, Hye-Ran Kim, Jung-Min Choi, Jupyo Hong, Yong-Suk Kim, Hyung-Seog Oh, Dae-Keun Han, Lee-Sup Kim
|
| High Speed Serial Interface for Mobile LCD Driver IC |
| IEEE International Symposium on Circuits and Systems , May 2008 |
| |
|
Jeonghyun Kim, Kyusik Chung, Young-Jun Kim, Seok-Hoon Kim, Lee-Sup Kim
|
| Clipping-Ratio-Independent 3D Graphics Clipping Engine by Dual-Thread Algorithm |
| IEEE International Symposium on Circuits and Systems , May 2008 |
| |
2007 |
|
Changhyo Yu, Kyusik Chung, Donghyun Kim, Lee-Sup Kim
|
| A 186Mvertices/s 161mW Floating-Point Vertex Processor for Mobile Graphics Systems |
| IEEE Custom Integrated Circuits Conference , Oct 2007 |
| |
|
Jae-Sung Yoon, Changhyo Yu, Donghyun Kim, Lee-Sup Kim
|
| Triangle-Level Depth Filter Method for Bandwidth Reduction in 3D Graphics Hardware |
| IEEE International Symposium on Circuits and Systems , May 2007 |
| |
|
Seok-Hoon Kim, Jae-Sung Yoon, Changhyo Yu, Donghyun Kim, Kyusik Chung, Lee-Sup Kim
|
| A 36fps SXGA 3D Display Processor with a Programmable 3D Graphics Rendering Engine |
| IEEE International Solid-State Circuit Conference , Feb 2007 |
| |
|
Byungguk Kim, Lee-Sup Kim
|
| A DLL with Jitter Reduction Techniques for DRAM Interfaces |
| IEEE International Solid-State Circuit Conference , Feb 2007 |
| |
2006 |
|
Jupyo Hong, Kyung-Soo Ha, Lee-Sup Kim
|
| A 0.18μm CMOS 10Gb/s 1:4 DEMUX Using Replica-Bias Circuits for Optical Receiver |
| IEEE International Symposium on Circuits and Systems , May 2006 |
| |
|
Seunghyun Cho, Changhyo Yu, Lee-Sup Kim
|
| An Efficient Texture Cache for Programmable Vertex Shaders |
| IEEE International Symposium on Circuits and Systems , May 2006 |
| |
|
Kwangil Oh, Seunghyun Cho, Lee-Sup Kim
|
| A Low Power SoC Bus with Low-leakage and Low-swing Technique |
| IEEE International Symposium on Circuits and Systems , May 2006 |
| |
|
Kyusik Chung, Changhyo Yu, Lee-Sup Kim
|
| A Vertex Cache of Programmable Geometry Processor for Mobile Multimedia Application |
| IEEE International Symposium on Circuits and Systems , May 2006 |
| |
|
Kyung-Soo Ha, Lee-Sup Kim
|
| A Charge-Pump reducing current mismatch in DLLs and PLLs |
| IEEE International Symposium on Circuits and Systems , May 2006 |
| |
|
Changhyo Yu, Lee-Sup Kim
|
| A 120Mvertices/s Multi-threaded VLIW Vertex Processor for Mobile Multimedia Applications |
| IEEE International Solid-State Circuit Conference , Feb 2006 |
| |
|
Byungguk Kim, Lee-Sup Kim
|
| A 20Gb/s 1:4 DEMUX Without Inductors in 0.13um CMOS |
| IEEE International Solid-State Circuit Conference , Feb 2006 |
| |
2005 |
|
Byungguk Kim, Kwangil Oh, Lee-Sup Kim
|
| A 500MHz DLL with Second Order Duty Cycle Corrector for Low Jitter |
| IEEE Cusotm Integrated Circuits Conference , Oct 2005 |
| |
|
Kyusik Chung, Donghyun Kim, Lee-Sup Kim
|
| A 3-way SIMD Engine for Programmable Triangle Setup in Embedded 3D Graphics Hardware |
| IEEE International Symposium on Circuits and Systems , May 2005 |
| |
|
Changhyo Yu, Donghyun Kim, Lee-Sup Kim
|
| A 33.2Mvertices/sec Programmable Geometry Engine for Multimedia Embedded System |
| IEEE International Symposium on Circuits and Systems , May 2005 |
| |
|
Jaewan Bae, Donghyun Kim, Lee-Sup Kim
|
| An 11M-Triangles/sec 3D Graphics Clipping Engine for Triangle Primitives |
| IEEE International Symposium on Circuits and Systems , May 2005 |
| |
|
Donghyun Kim, Kyusik Chung, Changhyo Yu, Chunho Kim, Inho Lee, Jaewan Bae, Joungyoun Kim, Lee-Sup Kim
|
| An SoC with 1.3Gtexels/sec 3-D Graphics Full Pipeline Engine for Consumer Applications |
| IEEE International Solid-State Circuit Conference , Feb 2005 |
| |
2004 |
|
Byungguk Kim, Lee-Sup Kim
|
| A 250MHz - 2GHz Wide Range Delay-Locked Loop |
| IEEE Custom Integrated Circuits Conference , Oct 2004 |
| |
|
Chunho Kim, Lee-Sup Kim
|
| Adaptive Selection of an Index in a Texture Cache |
| International Conference on Computer Design , Oct 2004 |
| |
|
Changhyo Yu, Lee-Sup Kim
|
| An Adaptive Spatial Filter for Early Depth Test |
| IEEE International Symposium on Circuits and Systems , May 2004 |
| |
|
Byungdo Yang, Lee-Sup Kim
|
| An Error Pattern ROM Compression Method for Continuous Data |
| IEEE International Symposium on Circuits and Systems , May 2004 |
| |
|
Donghyun Kim, Lee-Sup Kim
|
| Division-Free Rasterizer for Perspective-Correct Texture Filtering |
| IEEE International Symposium on Circuits and Systems , May 2004 |
| |
|
Kwangil Oh, Lee-Sup Kim
|
| A High Performance Low Power Dynamic PLA with Conditional Evaluation Scheme |
| IEEE International Symposium on Circuits and Systems , May 2004 |
| |
|
Kihyuk Sung, Lee-Sup Kim
|
| All-digital Fast-Locking Clock-Deskew Buffer Using a Hierarchical Phase Locking Delay |
| 제11회 한국반도체학술대회 , Feb 2004 |
| |
|
Byungdo Yang, Lee-Sup Kim
|
| A Low Power SRAM using Source Level Control Scheme |
| 제11회 한국반도체학술대회 , Feb 2004 |
| |
2003 |
|
Kwangil Oh, Lee-Sup Kim
|
| A Low Power Dynamic Programmable Logic Array (PLA) with Conditional Evaluation Scheme |
| SOC Design Conference , Nov 2003 |
| |
|
Kyusik Chung, Lee-Sup Kim
|
| ADAPTIVE TESSELLATION OF PN TRIANGLE WITH MODIFIED BRESENHAM ALGORITHM |
| SOC Design Conference , Nov 2003 |
| |
|
Changhyo Yu, Lee-Sup Kim
|
| An Adaptive Spatial Depth Filter for 3D Rendering IP |
| SOC Design Conference , Nov 2003 |
| |
|
Byungdo Yang, Lee-Sup Kim
|
| An Error Pattern ROM Compression Method for Continuous Data |
| SOC Design Conference, Nov 2003 |
| |
|
Donghyun Kim, Lee-Sup Kim
|
| An Implementation of Division-Free Rasterizer for Perspective-Correct Texture Filtering |
| SOC Design Conference , Nov 2003 |
| |
|
Changyoung Han, Yeonho Im, Lee-Sup Kim
|
| A Programmable High-Performance Geometry Engine |
| SOC Design Conference , Nov 2003 |
| |
|
Kwangil Oh, Lee-Sup Kim
|
| A Clock Delayed Sleep Mode Domino Logic for Wide Dynamic OR Gate |
| International Symposium on Low Power Electronics and Design , Aug 2003 |
| |
|
Byungdo Yang, Lee-Sup Kim
|
| A Low Power Charge Sharing Rom Using Dummy Bit Lines |
| IEEE International Symposium on Circuits and Systems , May 2003 |
| |
|
Inho Lee, Joungyoun Kim, Yeonho Im, Yunseok Choi, HyunChul Shin, Changyoung Han, Donghyun Kim, Hyoungjoon Park, Youngil Seo, Kyusik Chung, Changhyo Yu, Kanghyup Chun, Lee-Sup Kim
|
| A Hardware-like High-level Language Based Environment for 3D Graphics Architecture Exploration |
| IEEE International Symposium on Circuits and Systems, May 2003 |
| |
|
Kyusik Chung, Lee-Sup Kim
|
| A PN Triangle Generation Unit for Fast and Simple Tessellation Hardware |
| IEEE International Symposium on Circuits and Systems , May 2003 |
| |
|
Changhyo Yu, Lee-Sup Kim
|
| A Hierarchical Depth Buffer for Minimizing Memory Bandwidth in 3D Rendering Engine : DEPTH FILTER |
| IEEE International Symposium on Circuits and Systems , May 2003 |
| |
2002 |
|
Byungdo Yang, Lee-Sup Kim
|
| A ROM Compression Method for continuous data |
| IEEE Custom Integrated Circuits Conference , May 2002 |
| |
|
Youngjoon Kim, Kihyuk Sung, Lee-Sup Kim
|
| A 1.67 GHz Pipelined Carry-Select Adder Using the Complementary Scheme |
| IEEE International Symposium on Circuits and Systems , May 2002 |
| |
|
Kihyuk Sung, Byungdo Yang, Lee-Sup Kim
|
| Low Power Clock Generator Based on An Area-Reduced Interleaved Synchronous Mirror Delay Scheme |
| IEEE International Symposium on Circuits and Systems , May 2002 |
| |
|
Byungdo Yang, Lee-Sup Kim
|
| A High Speed Direct Digital Frequency Synthesizer Using A Low Power Pipelined Parallel Accumulator |
| IEEE International Symposium on Circuits and Systems , May 2002 |
| |
|
Byungdo Yang, Lee-Sup Kim
|
| A Low-Power ROM using Charge Recycling and Charge Sharing |
| IEEE International Solid-State Circuit Conference , Feb 2002 |
| |
|
Kihyuk Sung, Byungdo Yang, Lee-Sup Kim
|
| Low power clock generator based on an area-reduced interleaved synchronous mirror delay scheme |
| 제9회 한국반도체학술대회 , Feb 2002 |
| |
2001 |
|
Byungdo Yang, Kihyuk Sung, Youngjoon Kim, Lee-Sup Kim
|
| A Direct Digital Frequency Synthesizer Using A New ROM Compression Method |
| European Solid-State Circuits Conference , Sep 2001 |
| |
|
HyunChul Shin, Jinaeon Lee, Lee-Sup Kim
|
| SPAF:Sub-texel Precision Anistropic Filtering |
| Eurographics/SIGGRAPH Workshop on Graphics Hardware , Aug 2001 |
| |
|
Sunho Chang, Lee-Sup Kim
|
| Design Tradeoff in Merged DRAM Logic for Video Signal Processing |
| IEEE International Symposium on Circuits and Systems , May 2001 |
| |
|
Byungdo Yang, Lee-Sup Kim
|
| A low power charge recycling ROM architecture |
| IEEE International Symposium on Circuits and Systems , May 2001 |
| |
|
Hyunchoul Mo, Jongsun Kim, Lee-Sup Kim
|
| A high-speed pattern decodeer in MPEG-4 padding block hardware accelerator |
| IEEE International Symposium on Circuits and Systems , May 2001 |
| |
|
Youngjoon Kim, Lee-Sup Kim
|
| A low power carry select adder with reduced area |
| IEEE International Symposium on Circuits and Systems , May 2001 |
| |
2000 |
|
Kihyuk Sung, Lee-Sup Kim
|
| A NOR-type High-Speed Dual-Modulus Prescaler |
| International Conference on Signal Processing Applications & Technology , Oct 2000 |
| |
|
Byungdo Yang, Lee-Sup Kim
|
| High-Speed and Low-Swing On-Chip Bus Interface Using Threshold Voltage Driver and Dual Sense Amplifier Receiver |
| European Solid-State Circuits Conference , Sep 2000 |
| |
|
Jinaeon Lee, Lee-Sup Kim
|
| Single-Pass Full-Screen Hardware Accelerated Antialiasing |
| Eurographics/SIGGRAPH Workshop on Graphics Hardware , Jul 2000 |
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|
Joungyoun Kim, Lee-Sup Kim
|
| An Advenced Contrast Enhancement Using Partially Overlapped Sub-Block Histogram Equalizaion |
| IEEE International Symposium on Circuits and Systems , May 2000 |
| |
|
Sunho Chang, Jongsun Kim, Lee-Sup Kim
|
| Case Study: Testing of IP-based Mixed-Signal Fax/Modem System-on-chip |
| Design Automation and Test in Europe , Mar 2000 |
| |
|
Sunho Chang, Lee-Sup Kim
|
| A Memory Architecture with 4-Address Configurations for Video Signal Processing |
| Design Automation and Test in Europe , Mar 2000 |
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1999 |
|
Chunho Kim, Lee-Sup Kim
|
| High Speed Energy Efficient Master-Slave Flip-Flops |
| International Conference on VLSI and CAD , Dec 1999 |
| |
|
Youngsang Lee, Lee-Sup Kim
|
| Self-time Shared Division and Square-root Implementation using Full redundant Signed Digit Numbers |
| International Conference on VLSI and CAD , Dec 1999 |
| |
|
Youngmin Hong
|
| A Pipelined Row Address Decoding Scheme for Hierarchical Word Line Structure DRAM |
| International Conference on VLSI and CAD , Dec 1999 |
| |
|
Hosoek Lee, Bumsik Kim, Sunho Chang, Lee-Sup Kim
|
| A 250MHz Low Voltage Swing Bus Driver for Embedded Memory Logic |
| European Solid-State Circuits Conference , Sep 1999 |
| |
|
Chunho Kim, Hyoungjoon Park, Lee-Sup Kim
|
| A Low-Power Quadtree Fractal Image Decoder |
| European Solid-State Circuits Conference , Sep 1999 |
| |
|
Cheonho Bae, Sunho Chang, Bumsik Kim, Lee-Sup Kim
|
| Application Specific Embedded 8-Port SRAM with Simultaneous 256-bit Data Accessibility |
| Proceeding of Midwest Symposium on Circuits and Systems , Aug 1999 |
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1998 |
|
HyunChul Shin, Jinaeon Lee, Lee-Sup Kim
|
| A Minimized Hardware Architecture of Fast Phong Shader Using Taylor Series Approximation in 3D Graphics |
| IEEE International Conference on Computer Design: VLSI in Computer Processors , Oct 1998 |
| |
|
Seungkwon Paek, Hyunkyu Jeon, Lee-Sup Kim
|
| SEMI-RECURSIVE VLSI ARCHITECTURE FOR TWO DIMENSIONAL DISCRETE WAVELET TRANSFORM |
| IEEE International Symposium on Circuits and Systems , May 1998 |
| |
|
Kyunghoon Kim, Changyu Hong, Lee-Sup Kim
|
| VLSI IMPLEMENTATION OF DECODER FOR DECOMPRESSING FRACTAL-BASED COMPRESSED IMAGE |
| IEEE International Symposium on Circuits and Systems , May 1998 |
| |
|
HyunChul Shin, Jinaeon Lee, Lee-Sup Kim
|
| VLSI Implementation of Phong Shader in 3D Graphics |
| IEEE International Symposium on Circuits and Systems , May 1998 |
| |
|
Jinaeon Lee, Lee-Sup Kim
|
| 앤티알이아스드 다각형 묘화를 위한 래스터라이저의 하드웨어 구조 |
| Korean Conference on Semiconductors, Feb 1998 |
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1997 |
|
Bumsik Kim, Daehyun Chung, Lee-Sup Kim
|
| A New 4-2 Adder and Booth Selector for Low Power MAC Unit |
| Proceeding of International Symposium on Low Power Electronics and Design , Aug 1997 |
| |
|
Bumsik Kim, Lee-Sup Kim
|
| IRAM Design for Multimedia Applications |
| Workshop on Mixing Logic and DRAM: Chips that compute and remember, Denver , Jun 1997 |
| |
|
Bumsik Kim, Lee-Sup Kim
|
| A Low Power 100MHz All digital Delay-Locked Loop |
| IEEE International Symposium on Circuits and Systems , Jun 1997 |
| |
1996 |
|
Bumsik Kim, Lee-Sup Kim
|
| Low Power Pipelined FFT Architecture for Synthetic Aperture Radar Signal Processing |
| Proceeding of Midwest Symposium on Circuits and Systems , Aug 1996 |
| |
|
Yun-Cheol Jeong, H.S. Soh, Lee-Sup Kim
|
| A Design of Crosstalk Compensation Circuit in TFT-LCDs |
| Digest of SID 96 , Jun 1996 |
| |
|
Seungkwon Paek, Ji-Heub Kim, Byungsup Kwon, Daehyun Chung, Lee-Sup Kim
|
| A Mode-Changeable 2-D DCT/IDCT Processor for Digital VCR |
| Processing of IEEE Consumer Electronics Conference , Jun 1996 |
| |
1995 |
|
Ji-Heub Kim, Lee-Sup Kim
|
| An ASIC implementation of RCM algorithms for Synthetic Radar Signal Processing |
| Proceedings of IEEE Workshop on VLSI Signal Processing , Oct 1995 |
| |
1994 |
|
|
| 완전 탐색 블럭정합 움직임 추정기에서의 변위 벡터 추출을 위한 효율적인 논리회로의 구현 |
| 전자공학회 1994년도 추계종합학술대회논문집, 제 17권 제 2호 , Nov 1994 |
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1993 |
|
|
| 한개의 1-D DCT 모듈만을 이용한 고속 2-D DCT프로세서의 구조 |
| 통신학회 1993년도 추계종합학술대회논문집, 제 12권 제 2호 , Nov 1993 |
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