HIGHLIGHTS
  • Award
    2017 IDEC SoC Congress Chip Design Contest Best Design Award
  • Research
    ISSCC 2016 CNN Chip Featured in IEEE Spectrum April 2016 Issue
  • Award
    2014 IDEC SoC Congress Chip Design Contest Best Design Award
  • Award
    The 32nd IEEE ICCD Best Paper Award
  • Research
    A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth

Chong-soo Jung, Dong-il Lee and Dae-woong Lee(Advisor Lee-Sup Kim) received “Best Design Award” in 2017 IDEC SoC Congress Chip Design Contest.

Related paper: "A DLL-based Reference-less CDR with ISI Jitter Reduction Scheme " by Chongsoo Jung

Our Convolutional Neural Network(CNN) chip presented at ISSCC 2016 is covered in the article "Neural Networks on the Go" in the IEEE Spectrum April 2016 Issue.

Related paper: "A 1.42TOPS/W Deep Convolutional Neural Network Recognition Processor for Intelligent IoE Systems" by Jaehyeong Sim

Yong-Hun Kim, Young-Ju Kim, and Tae-Ho Lee (Advisor Lee-Sup Kim) received “Best Design Award” in 2014 IDEC SoC Congress Chip Design Contest.

Related paper: "A 21Gb/s, 1.63pJ/bit Adaptive CTLE and 1-tap DFE with Single Loop Spectrum Balancing Method in 65nm CMOS" by Yong-Hun Kim

Jaehyeong Sim, Jun-Seok Park, and Seungwook Paek (Advisor Lee-Sup Kim) received “Best Paper Award” in The 32nd IEEE International Conference on Computer Design.

Related paper: "Timing Error Masking by Exploiting Operand Value Locality in SIMD Architecture" by Jaehyeong Sim

A source synchronous architecture with constant and wide jitter-tracking bandwidth (JTB) is presented. The proposed receiver is based on an injection-locked oscillator (ILO), which provides jitter filtering and phase deskew simultaneously. While using only the ILO has intrinsic two dependence problems (JTB versus deskew and JTB versus a voltage-controlled oscillator tuning range required for 1 unit interval deskew), the proposed receiver makes them independent. Therefore, the proposed receiver can achieve the optimal JTB in a wide range by controlling deskew phase and JTB independently. A test chip was implemented to prove 11Gb/s data recovery with constant 70MHz to 1GHz JTB in 0.13μm CMOS.

Related paper: "A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth" by Sang-Hye Chung

Video

Demonstration video of object classification from 32x32 input images using our CNN chip.

Demonstration viedo of image classification from 28 x 28 handwritten digit images using FPGA.

Latest News

July 5, 2018

심재형 씨의 논문이 ACM/IEEE International Conference on Computer Aided Design에 게재 승인되었습니다. Read More

May 12, 2018

설호석씨의 논문이 IEEE Transactions on Computers 에 게재 승인 되었습니다. Read More

May 12, 2018

최승규씨의 논문이 ACM/IEEE International Symposium on Low Power Electronics and Design 에 게재 승인 되었습니다. Read More

May 12, 2018

5월 12일에 연구실 홈커밍 행사가 있었습니다. Read More

Feb. 28, 2018

2018년 신입생 환영회 및 졸업생 송별회가 있었습니다. Read More

Feb. 23, 2018

2018년 졸업식이 있었습니다. Read More

Oct. 15, 2017

이동일씨의 논문이 IEEE Transactions on Circuits and Systems II 에 게재 승인 되었습니다. Read More

Sept. 28, 2017

김용훈씨의 논문이 IEEE Transactions on Circuits and Systems II 에 게재 승인 되었습니다.
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July 31, 2017

설호석씨의 논문이 TVLSI에 accept 되었습니다.
*제목: In-DRAM data initialization
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July 1, 2017

우리 연구실에서 강원도 정선으로 여름 MT를 다녀왔습니다.
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Recently Accepted Papers

Conference (to be presented)

Jaehyeong Sim, Hoseok Seol, Lee-Sup Kim
NID: Processing Binary Convolutional Neural Network in Commodity DRAM
ACM/IEEE International Conference On Computer Aided Design, 2018
 
Seungkyu Choi, Jaehyeong Sim, Myeonggu Kang, Lee-Sup Kim
TrainWare: A Memory Optimized Weight Update Architecture for On-Device Convolutional Neural Network Training
ACM/IEEE International Symposium on Low Power Electronics and Design, 2018