| International Journal Papers |
| Daewoong Lee, Dongil Lee, Yong-Hun Kim, Hyunkyu Jeon, Byungguk Kim, Lee-Sup Kim |
| A 10.8 Gb/s Quarter-Rate 1 FIR 1 IIR Direct DFE with Non-Time-Overlapping Data Generation for 4:1 CMOS Clockless Multiplexer |
| IEEE Transactions on Circuits and Systems II: Express Briefs, 2020 |
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| Byungguk Kim, Lee-Sup Kim |
| A DLL with Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces |
| IEEE Journal of Solid-State Circuits , 2009 |
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| Byungguk Kim, Lee-Sup Kim |
| A 20Gb/s 1:4 DEMUX without Inductors and Low-Power Divide-by-2 Circuit in 0.13um CMOS Technology |
| IEEE Journal of Solid-State Circuits , 2008 |
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| Byungguk Kim, Lee-Sup Kim |
| A 250-MHz-2-GHz Wide-Range Delay-Locked Loop |
| IEEE Journal of Solid-State Circuits , 2005 |
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| International Conference Papers |
| Byungguk Kim, Lee-Sup Kim |
| A DLL with Jitter Reduction Techniques for DRAM Interfaces |
| IEEE International Solid-State Circuit Conference , 2007 |
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| Byungguk Kim, Lee-Sup Kim |
| A 20Gb/s 1:4 DEMUX Without Inductors in 0.13um CMOS |
| IEEE International Solid-State Circuit Conference , 2006 |
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| Byungguk Kim, Kwangil Oh, Lee-Sup Kim |
| A 500MHz DLL with Second Order Duty Cycle Corrector for Low Jitter |
| IEEE Cusotm Integrated Circuits Conference , 2005 |
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| Byungguk Kim, Lee-Sup Kim |
| A 250MHz - 2GHz Wide Range Delay-Locked Loop |
| IEEE Custom Integrated Circuits Conference , 2004 |
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