| International Journal Papers |
| Daewoong Lee, Dongil Lee, Yong-Hun Kim, Hyunkyu Jeon, Byungguk Kim, Lee-Sup Kim |
| A 10.8 Gb/s Quarter-Rate 1 FIR 1 IIR Direct DFE with Non-Time-Overlapping Data Generation for 4:1 CMOS Clockless Multiplexer |
| IEEE Transactions on Circuits and Systems II: Express Briefs, 2020 |
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| Chongsoo Jung, Dongil Lee, Yong-Hun Kim, Daewoong Lee, Lee-Sup Kim |
| A 12 Gb/s 1.59 mW/Gb/s Input-Data-Jitter-Tolerant Injection-Type CDR with Super-Harmonic Injection-Locking in 65 nm CMOS |
| IEEE Transactions on Circuits and Systems II, 2019 |
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| Daewoong Lee, Dongil Lee, Yong-Hun Kim, Lee-Sup Kim |
| A 0.9-V 12-Gb/s 2-FIR Tap Direct DFE with Feedback-Signal Common-Mode-Control |
| IEEE Transactions on Very Large Scale Integration, 2019 |
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| Dongil Lee, Yong-Hun Kim, Daewoong Lee, Lee-Sup Kim |
| A 0.65V, 11.2Gb/s Power Noise Tolerant Source-synchronous Injection-locked Receiver with Direct DTLB DFE |
| IEEE Transactions on Circuits and Systems II, 2018 |
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| Yong-Hun Kim, Dongil Lee, Daewoong Lee, Lee-Sup Kim |
| A 10 Gb/s Reference-Less Baud-Rate CDR for Low Power Consumption with Direct Feedback Method |
| IEEE Transactions on Circuits and Systems II, 2018 |
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| Yong-Hun Kim, Taeho Lee, Hyunkyu Jeon, Dongil Lee, Lee-Sup Kim |
| An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-less Digital CDR for LCD Intra-Panel Interface |
| IEEE Transactions on Circuits and Systems I, 2017 |
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| Taeho Lee, Yong-Hun Kim, Lee-Sup Kim |
| A 5 Gb/s Digital Clock and Data Recovery Circuit with Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network |
| IEEE Transactions on Very Large Scale Integration Systems, 2017 |
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| Taeho Lee, Yong-Hun Kim, Jaehyeong Sim, Jun-Seok Park, Lee-Sup Kim |
| A 5 Gb/s 2.67 mW/Gb/s Digital Clock and Data Recovery with Hybrid Dithering Using a Time-Dithered Delta-Sigma Modulator |
| IEEE Transactions on Very Large Scale Integration Systems, 2016 |
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| Sang-Hye Chung, Young-Ju Kim, Yong-Hun Kim, Lee-Sup Kim |
| A 10Gb/s 0.71pJ/bit Forwarded-Clock Receiver Tolerant to High Frequency Jitter in 65nm CMOS |
| IEEE Transactions on Circuits and Systems II, 2016 |
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| Yong-Hun Kim, Young-Ju Kim, Taeho Lee, Lee-Sup Kim |
| A 21Gb/s 1.63pJ/bit Adaptive CTLE and 1-tap DFE with Single Loop Spectrum Balancing Method |
| IEEE Transactions on Very Large Scale Integration Systems, 2016 |
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| Yong-Hun Kim, Young-Ju Kim, Taeho Lee, Lee-Sup Kim |
| An 11.5 Gb/s 1/4th Baud-Rate CTLE and Two-Tap DFE With Boosted High Frequency Gain in 110-nm CMOS |
| IEEE Transactions on Very Large Scale Integration Systems , 2015 |
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| International Conference Papers |
| Daewoong Lee, Dongil Lee, Yong-Hun Kim, Lee-Sup Kim |
| A 0.87 V 12.5 Gb/s Clock-Path Feedback Equalization Receiver with Unfixed Tap Weighting Property in 65 nm CMOS |
| Symposium on VLSI Circuits, 2019 |
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| Dongil Lee, Taeho Lee, Yong-Hun Kim, Young-Ju Kim, Lee-Sup Kim |
| An Injection Locked PLL for Power Supply Variation Robustness Using Negative Phase Shift Phenomenon of Injection Locked Frequency Divider |
| IEEE Custom Integrated Circuits Conference, 2015 |
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| Daewoong Lee, Dongil Lee, Taeho Lee, Yong-Hun Kim, Lee-Sup Kim |
| An Integrated Time Register and Arithmetic Circuit with Combined Operation for Time-Domain Signal Processing |
| IEEE International Symposium on Circuits and Systems, 2015 |
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| Yong-Hun Kim, Lee-Sup Kim |
| A 20 Gbps 1-Tap Decision Feedback Equalizer with Unfixed Tap Coefficient |
| IEEE International Symposium on Circuits and Systems, 2012 |
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