| International Journal Papers |
| Yong-Hun Kim, Taeho Lee, Hyunkyu Jeon, Dongil Lee, Lee-Sup Kim |
| An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-less Digital CDR for LCD Intra-Panel Interface |
| IEEE Transactions on Circuits and Systems I, 2017 |
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| Taeho Lee, Yong-Hun Kim, Lee-Sup Kim |
| A 5 Gb/s Digital Clock and Data Recovery Circuit with Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network |
| IEEE Transactions on Very Large Scale Integration Systems, 2017 |
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| Dongil Lee, Taeho Lee, Young-Ju Kim, Lee-Sup Kim |
| A 21% Jitter Improved Self-aligned Divider-less Injection-Locked PLL with a VCO Control Voltage Ripple Compensated Phase Detector |
| IEEE Transactions on CAS II, 2016 |
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| Taeho Lee, Yong-Hun Kim, Jaehyeong Sim, Jun-Seok Park, Lee-Sup Kim |
| A 5 Gb/s 2.67 mW/Gb/s Digital Clock and Data Recovery with Hybrid Dithering Using a Time-Dithered Delta-Sigma Modulator |
| IEEE Transactions on Very Large Scale Integration Systems, 2016 |
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| Yong-Hun Kim, Young-Ju Kim, Taeho Lee, Lee-Sup Kim |
| A 21Gb/s 1.63pJ/bit Adaptive CTLE and 1-tap DFE with Single Loop Spectrum Balancing Method |
| IEEE Transactions on Very Large Scale Integration Systems, 2016 |
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| Yong-Hun Kim, Young-Ju Kim, Taeho Lee, Lee-Sup Kim |
| An 11.5 Gb/s 1/4th Baud-Rate CTLE and Two-Tap DFE With Boosted High Frequency Gain in 110-nm CMOS |
| IEEE Transactions on Very Large Scale Integration Systems , 2015 |
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| International Conference Papers |
| Dongil Lee, Taeho Lee, Yong-Hun Kim, Young-Ju Kim, Lee-Sup Kim |
| An Injection Locked PLL for Power Supply Variation Robustness Using Negative Phase Shift Phenomenon of Injection Locked Frequency Divider |
| IEEE Custom Integrated Circuits Conference, 2015 |
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| Daewoong Lee, Dongil Lee, Taeho Lee, Yong-Hun Kim, Lee-Sup Kim |
| An Integrated Time Register and Arithmetic Circuit with Combined Operation for Time-Domain Signal Processing |
| IEEE International Symposium on Circuits and Systems, 2015 |
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