In the high speed chip-to-chip communications, much effort has been made toward compensating for severe inter-symbol interference (ISI). As increasing the data rate, the channel loss becomes severe, so dispersion occurs. This dispersion causes the ISI. Feed forward equalizers (FFEs) continuous time linear equalizers (CTLEs) and decision feedback equalizers (DFEs) are widely used to solve the ISI problem in the chip-to-chip communications.

For the FFE and CTLE, it consumes low power compared to the DFE or other digital methods, but it also increases noise. Thus, the optimum compensating is required not to do over compensation or under compensation.

There are some issues to be addressed for the DFE. The first is that there is 1UI feedback loop timing problem for the DFE. In response to this problem, data interleaving and speculation methods have been proposed, but 1UI timing margin remains as the bottleneck of the DFE for very high speed serial links. Also it consumes huge power compared to CTLE or FFE structure, so it should be solved.